Conventional methods for forming a metal interconnect structure may include:
referring to FIG. 1, providing a semiconductor substrate 100, forming an dielectric layer 101 on the semiconductor substrate 100, and forming a metal layer 102 on the dielectric layer 101;
referring to FIG. 2, forming a patterned photoresist layer on the metal layer 102 and etching the metal layer 102 by taking the patterned photoresist layer as a mask to form a groove 103, the metal layer 102 on two sides of the groove 103 forming metal interconnects; and
referring to FIG. 3, depositing an intermetallic dielectric layer 104 which fills the groove 103 and covers the metal layer 102.
However, when technology node is developed to less than 90 nm, the distance between adjacent metal interconnects becomes shorter and parasitic capacitance generated therebetween becomes greater. The parasitic capacitance may not only affect a running speed of a chip but also reduce the reliability of devices on the chip. To alleviate the problem, materials with a high dielectric constant, such as silicon dioxide are replaced with low-K dielectric materials to form an interlayer dielectric layer and an intermetallic dielectric layer in semiconductor processes, which may reduce parasitic capacitance between adjacent metal interconnects. When technology node is developed to less than 32 nm, low-K dielectric materials may not have a good performance on reducing parasitic capacitance. Besides, even in processes with technology node of more than 90 nm, the conventional method of filling a groove between adjacent metal interconnects with an intermetallic dielectric layer, such as some radio frequency integrated circuits, cannot meet the technique requirement of minimizing parasitic capacitance between two adjacent metal interconnects.
To obtain more relative information of methods for forming a metal interconnect structure, please refer to US patent publication No. US2011/0018091A1.